Not Applicable.
Not applicable.
The invention is in the field of integrated circuit manufacture, and is more specifically directed to the formation of conductor layers in such circuits.
As is well-known in the art, the trend toward ever-shrinking feature sizes in modern integrated circuits is continuing, providing dramatic increases in functionality and decreased manufacturing cost over time. This decrease in feature size results in a corresponding decrease in the cross-sectional area of integrated circuit conductor elements, and thus a decrease in conductance of these elements, considering that conductance is directly proportional to the cross-sectional area of the conductor. It is therefore necessary to compensate for this decrease in conductance in order for device performance to remain the same or better, as manufacturing technologies improve.
To provide this increased conductivity, copper has become a popular metal for integrated circuit conductors, replacing aluminum metallization. Besides copper being significantly more conductive than aluminum, copper is also much less vulnerable to the electromigration failure than is aluminum. Because electromigration is also dependent upon current density, which of course increases for constant current as the cross-sectional area of the conductor decreases, copper not only provide improved conductivity over a similarly sized aluminum conductor, but can also support a higher current density, from an electromigration standpoint, than can an aluminum conductor.
Unfortunately, the manufacturing processes required to fabricate copper conductors are more complex and less robust than are the manufacturing processes for aluminum metallization. In modern integrated circuits, a damascene process is often used to form copper conductors. In this approach, trenches or vias are first formed in an insulator layer, following which a layer of copper is deposited, typically by electrochemical deposition (e.g., electroplating). Chemical-mechanical polishing (CMP) is then performed to remove the excess copper from the surface of the insulator, leaving the copper conductor inlaid within the via. While this processing is necessarily more cumbersome than conventional sputtering or evaporation of aluminum metal, additional problems are also presented by the implementation of copper conductors. One problem is the poisoning of minority carrier lifetimes that occurs if copper atoms diffuse into the underlying silicon from the copper metallization.
Another particularly troublesome problem is the relatively poor and inconsistent adhesion between copper metallization and the underlying layers. If adhesion is especially poor, the copper conductor can rip out of the via during the CMP step in the damascene process, rendering the integrated circuit nonfunctional. Poor adhesion can also cause voids in the copper conductors, presenting long term reliability issues.
A known approach to improve adhesion and also limit copper diffusion is to include a liner layer under the deposited copper. This liner layer, which may be a combination of layers of different materials, preferably includes a diffusion barrier to copper, and also preferably adheres strongly to both the underlying insulator layer and the overlying copper metallization. Edelstein et al., xe2x80x9cA High Performance Liner for Copper Damascene Interconnectsxe2x80x9d, Proceedings of the IEEE 2001 International Interconnect Technology Conference (IEEE, 2001), pp. 9-11, describes a liner layer that includes a layer of tantalum nitride (TaN) underlying a layer of tantalum metal (Ta). According to this approach, the overlying Ta layer is formed by turning off the nitrogen sputtering gas after the desired thickness of TaN has been sputtered from a tantalum target, over an underlying silicon dioxide dielectric. This article claims good adhesion of the liner and copper system to the underlying oxide.
Reduced feature sizes in integrated circuits also reduce the electrical isolation among the various metal conductors. In modern integrated circuits, electrical isolation between adjacent conductors in the same metallization xe2x80x9clevelxe2x80x9d, and also among conductors in adjacent metallization levels, must be adequate. Electrical isolation is even more problematic because of the planarization of each conductor level, to maximize step coverage of the conductors, and also to ensure accurate patterning, given the extremely shallow depths of focus available for deep UV photolithography of these small features.
Improvements in the dielectric isolation properties have been attained by using dielectric materials having a lower dielectric constant than conventional silicon dioxide. These materials include fluorine-doped silicon dioxide (also referred to as fluorinated silicate glass, or FSG), organosilicate glass (OSG), and other materials, such as SiLK dielectric material available from Dow Chemical Co., the Zirkon LK series of spin-on dielectric materials available from Shipley Company L.L.C., aerogel, xerogel, and other conventional low-k insulator materials. It is desirable to use these low-k dielectric materials in combination with high current conductors, such as copper interconnects, as described above.
It has been observed, in connection with this invention, that conventional liner layers do not provide adequate adhesion, especially when applied to low-k dielectrics. Specifically, it has been observed that the TaN/Ta bilayer liner, such as described in the Edelstein paper, has weak adhesion at the interface between TaN and the underlying dielectric. The adhesion in this system has also been observed to vary widely from wafer to wafer, indicating a run order effect within a lot. It is believed, according to this invention, that this poor adhesion of the TaN/Ta bilayer is due to the depletion of nitrogen in the sputtering chamber that results from the turning off of nitrogen sputtering gas for the previous wafer.
Other methods of improving the adhesion of a TaN/Ta bilayer liner to a low-k dielectric have been considered. One such approach is the deposition of a silicon dioxide cap over the low-k dielectric, to which the TaN/Ta bilayer liner adheres relatively well. While this approach may improve adhesion at the top surface of the dielectric, no oxide cap on can be formed the sidewalls of vias or trenches etched through the dielectric layer, so that the adhesion of the copper system will still be weak at those locations. The oxide cap cannot be formed after via or trench etch, of course, without severely limiting the size of the via or trench. Cleanup approaches, such as a hydrogen/helium reactive sputtering etch clean, may or may not improve adhesion, but will definitely require new hardware and an additional chamber.
It is therefore an object of this invention to provide an integrated circuit structure, and a method of making the same, having improved adhesion of copper metallization to low-dielectric-constant dielectric layers.
It is a further object of this invention to provide such a structure and method that does not require additional process chambers for implementation.
It is a further object of this invention to provide copper conductors with a low likelihood of voiding.
It is a further object of this invention to provide such a method that is repeatable and consistent from wafer to wafer in the manufacturing process.
Other objects and advantages of this invention will be apparent to those of ordinary skill in the art having reference to the following specification together with its drawings.
The present invention may be implemented by exposing the surface of a low-dielectric-constant dielectric to nitrogen, after the etching of trenches and vias. This exposure can be implemented by introducing nitrogen gas prior to liner layer deposition. This nitrogen treatment can be supplemented by a nitrogen plasma treatment of the surface of the low-k dielectric. Subsequent sputter deposition of tantalum nitride, followed by tantalum sputtering, results in a TaN/Ta bilayer liner that adheres extremely well to the low-k dielectric. Copper conductors are then formed into the trenches and vias, and polished by chemical mechanical polishing (CMP) to form the copper conductors in the damascene manner. Excellent adhesion is obtained.